On Mon, Mar 27, 2023 at 02:13:05PM +0200, Arnd Bergmann wrote:
From: Arnd Bergmann <arnd@xxxxxxxx> For a DMA_BIDIRECTIONAL transfer, the caches have to be cleaned first to let the device see data written by the CPU, and invalidated after the transfer to let the CPU see data written by the device. riscv also invalidates the caches before the transfer, which does not appear to serve any purpose.
Rationale makes sense to me.. Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Thanks for working on all of this Arnd!
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