From: Christophe Leroy
Sent: 30 June 2022 10:40
Le 30/06/2022 à 10:04, David Laight a écrit :
From: Michael Schmitz
Sent: 29 June 2022 00:09
Hi Arnd,
On 29/06/22 09:50, Arnd Bergmann wrote:
On Tue, Jun 28, 2022 at 11:03 PM Michael Schmitz <schmitzmic@xxxxxxxxx> wrote:
On 28/06/22 19:03, Geert Uytterhoeven wrote:
The driver allocates bounce buffers using kmalloc if it hits an
unaligned data buffer - can such buffers still even happen these days?
No idea.
Hmmm - I think I'll stick a WARN_ONCE() in there so we know whether this
code path is still being used.
kmalloc() guarantees alignment to the next power-of-two size or
KMALLOC_MIN_ALIGN, whichever is bigger. On m68k this means it
is cacheline aligned.
And all SCSI buffers are allocated using kmalloc? No way at all for user
space to pass unaligned data?
I didn't think kmalloc() gave any such guarantee about alignment.
I does since commit 59bb47985c1d ("mm, sl[aou]b: guarantee natural
alignment for kmalloc(power-of-two)")
Looks like it is done for 'power-of-two' less than PAGE_SIZE.
This may not help scsi tape writes which could easily be (say) 47 bytes.
I think that only guarantees 2 byte alignment on m68k.
(Although increasing the min-alignment on m68k to 4 (or even 8)
will probably make no measurable difference.)
What happens above PAGE_SIZE?
Any structure with a trailing [] field could easily request
'64k + a_bit' bytes.
You don't really want to extend this to 128k - but I suspect
that is what happens.
David
Christophe
There are cache-line alignment requirements on systems with non-coherent
dma, but otherwise the alignment can be much smaller.
One of the allocators adds a header to each item, IIRC that can
lead to 'unexpected' alignments - especially on m68k.
dma_alloc_coherent() does align to next 'power of 2'.
And sometimes you need (eg) 16k allocates that are 16k aligned.
David
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