On Mon, 18 Apr 2022, Thomas Bogendoerfer wrote:
Also the systems I have in mind and that lack a counter in the chipset
actually can make use of the buggy CP0 timer, because it's only when CP0
timer interrupts are used that the erratum matters, but they use a DS1287
RTC interrupt instead unconditionally as the clock event (see the comment
at the bottom of arch/mips/dec/time.c). But this has not been factored in
with `can_use_mips_counter' (should it just check for `mips_hpt_frequency'
being zero perhaps, meaning the timer interrupt not being used?).
Thomas, do you happen to know if any of the SGI systems that we support
had buggy early R4k chips?
IP22 has probably seen all buggy MIPS chips produced, so yes I even own
Indy/Indigo2 CPU boards with early R4k chips.
Do they actually use the CP0 timer as a clock event device? Do they have
an alternative high-precision timer available?
In the course of verifying this change I have noticed my DECstation
5000/260, which has a high-precision timer in the chipset available as a
clock source device, does register the CP0 timer as a clock source device
regardless. Upon a closer inspection I have noticed that the CP0 timer
interrupt is non-functional in this machine, which I have then confirmed
as a valid CPU hardware configuration via the TimIntDis/TimerIntDis (the
R4k CPU manual is inconsistent in naming here) boot-mode bit. It allows
IP7 to be used as an external interrupt source instead. I used not to be
aware of the presence of this boot-mode bit.
I find this arrangement odd, because IP7 used to be wired internally as
the FPU interrupt with the 5000/240's CPU module, so it's not usable as an
external interrupt anyway with this system's mainboard.
That means however that this machine (and possibly the 5000/150 as well,
but I'll have to verify that once I get at the KN04 CPU module I have in a
drawer at my other place) can use the CP0 timer as a clock source device
unconditionally. I think this discovery asks for code optimisation, which
I'll try to cook up sometime.
I don't expect the IP22 to have a similar arrangement with the CP0 timer
interrupt given that the CPU was an in-house design at SGI, but who knows?
Do you?
Maciej
