On Mon, 14 Mar 2022 14:30:18 +0100 Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
On Mon, Mar 7, 2022 at 9:53 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:Introduce fourcc codes for color-indexed frame buffer formats with two, four, and sixteen colors, and provide a mapping from bit per pixel and depth to fourcc codes. As the number of bits per pixel is less than eight, these rely on proper block handling for the calculation of bits per pixel and pitch. Signed-off-by: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>--- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -99,7 +99,10 @@ extern "C" { #define DRM_FORMAT_INVALID 0 /* color index */ -#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ +#define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */ +#define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */ +#define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */ +#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C 8 one pixel/byte */ /* 8 bpp Red */ #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */After replying to Ilia's comment[1], I realized the CFB drawing operations use native byte and bit ordering, unless FBINFO_FOREIGN_ENDIAN is set. While Amiga, Atari, and Sun-3 use big-endian bit ordering, e.g. Acorn VIDC[2] uses little endian, and SH7760[3] is configurable (sh7760fb configures ordering to match host order). BTW, ssd130{7fb,x}_update_rect() both assume little-endian, so I guess they are broken on big-endian. Fbtest uses big-endian bit ordering, so < 8 bpp is probably broken on little-endian. Hence the above should become: #define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C7:C6:C5:C4:C3:C2:C1:C0 1:1:1:1:1:1:1:1 eight pixels/byte */ #define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C3:C2:C1:C0 2:2:2:2 four pixels/byte */ #define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C1:C0 4:4 two pixels/byte */ The same changes should be made for DRM_FORMAT_[RD][124]. The fbdev emulation code should gain support for these with and without DRM_FORMAT_BIG_ENDIAN, the latter perhaps only on big-endian platforms? [1] https://lore.kernel.org/r/CAKb7UvgEdm9U=+RyRwL0TGRfA_Qc7NbhCWoZOft2DKdXggtKYw@xxxxxxxxxxxxxx/ [2] See p.30 of the VIDC datasheet http://chrisacorns.computinghistory.org.uk/docs/Acorn/Misc/Acorn_VIDC_Datasheet.pdf [3] See p.1178 of the SH7660 datasheet https://datasheet.octopart.com/HD6417760BL200AV-Renesas-datasheet-14105759.pdf
Hi Geert, why would CPU endianess affect the order of bits in a byte? Do you mean that bit 0 one machine is (1 << 0), and on another machine bit 0 is (1 << 7)? In C, we have only one way to address bits of a byte and that is with arithmetic. You cannot take the address of a bit any other way, can you? Can we standardise on "bit n of a byte is addressed as (1 << n)"? I don't mind in which order the pixels are inside a byte, as long as it doesn't change by CPU endianess. If you need both directions, then use two different drm_fourcc codes that do not change their meaning by CPU endianess. Just like we have XRGB and BGRX formats. I would not like to see DRM_FORMAT_BIG_ENDIAN used for this, it would conflate a whole new concept into the mess that is little- vs. big-endian. Thanks, pq
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