On Mon, Apr 29, 2019 at 10:44 AM Geert Uytterhoeven
<geert@xxxxxxxxxxxxxx> wrote:
On Sun, Apr 28, 2019 at 3:59 PM Greg Ungerer <gerg@xxxxxxxxxxxxxx> wrote:
On 28/4/19 7:21 pm, Arnd Bergmann wrote:
On Sun, Apr 28, 2019 at 10:46 AM Geert Uytterhoeven
<geert@xxxxxxxxxxxxxx> wrote:
Orthogonal to how Coldfire's read[wl]() should be fixed, I find it a bit
questionable to swap data twice on big endian architectures.
I would expect that the compiler is capable of detecting a double
swap and optimize it out. Even if it can't, there are not that many
instances of io{read,write}{16,32}be in the kernel, so the increase
in kernel image size from a double swap should be limited to a
few extra instructions, and the runtime overhead should be
negligible compared to the bus access.
Probably the overhead is not negligible on old m68k...
Maybe the I/O devices are faster than I expected then. I was guessing
that there is still a factor of 100x or more between going to an on-chip
bus and single byterev register-to-register instruction.
I did notice that __arch_swab32() is an inline assembly, so the
compiler has no way of eliminating the double swap, but
setting CONFIG_ARCH_USE_BUILTIN_BSWAP makes it
do the right thing.
Arnd
