For coldfire with MMU enabled, data cache did not follow the configuration but was configured in writethrough mode. Signed-off-by: Stany MARCEL <stany.marcel@xxxxxxxxxxxxxxxxxxxxxx> --- arch/m68k/include/asm/m54xxacr.h | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index cac5bcd..8f932be 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -94,25 +94,18 @@ * register region as non-cacheable. And then we map all our RAM as * cacheable and supervisor access only. */ -#ifndef CONFIG_M54xx_DMA_ZONE - -#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \ +#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \ ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP) +#if defined(CONFIG_CACHE_COPYBACK) #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ - ACR_ENABLE+ACR_SUPER+ACR_SP) + ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP) +#else +#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ + ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT) +#endif #define ACR2_MODE 0 #define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ ACR_ENABLE+ACR_SUPER+ACR_SP) - -#else - -#define ACR0_MODE 0xF00FA048 -#define ACR1_MODE 0x000FA028 -#define ACR2_MODE 0x00000000 -#define ACR3_MODE 0x000FA028 - -#endif /* CONFIG_M54xx_DMA_ZONE */ - #else /* -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
