From: Greg Ungerer <gerg@xxxxxxxxxxx>
The ColdFire MMU has separate read and write bits, unlike the Motorola
m68k MMU which has a single read-only bit.
Define a _PAGE_READWRITE value for the Motorola MMU, which is 0, so we
can unconditionaly include that in the page table entry bits when setting
up ioremapped pages.
Signed-off-by: Greg Ungerer <gerg@xxxxxxxxxxx>
Acked-by: Matt Waddel <mwaddel@xxxxxxxxx>
Acked-by: Kurt Mahan <kmahan@xxxxxxxxxxxx>
---
arch/m68k/include/asm/motorola_pgtable.h | 1 +
arch/m68k/mm/kmap.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/m68k/include/asm/motorola_pgtable.h b/arch/m68k/include/asm/motorola_pgtable.h
index 45bd3f5..e0fdd4d 100644
--- a/arch/m68k/include/asm/motorola_pgtable.h
+++ b/arch/m68k/include/asm/motorola_pgtable.h
@@ -8,6 +8,7 @@
#define _PAGE_PRESENT 0x001
#define _PAGE_SHORT 0x002
#define _PAGE_RONLY 0x004
+#define _PAGE_READWRITE 0x000
#define _PAGE_ACCESSED 0x008
#define _PAGE_DIRTY 0x010
#define _PAGE_SUPER 0x080 /* 68040 supervisor only */
diff --git a/arch/m68k/mm/kmap.c b/arch/m68k/mm/kmap.c
index 6934584..1cc2bed 100644
--- a/arch/m68k/mm/kmap.c
+++ b/arch/m68k/mm/kmap.c
@@ -171,7 +171,8 @@ void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cachefla
break;
}
} else {
- physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
+ physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED |
+ _PAGE_DIRTY | _PAGE_READWRITE);
switch (cacheflag) {
case IOMAP_NOCACHE_SER:
case IOMAP_NOCACHE_NONSER:
--
1.7.0.4
--
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