On Fri, 24 Nov 2023, GaryWang 汪之逸 wrote: > Hi Andy, > > Thank you for review the V7 patch and sorry for my poor English, for your question, please kindly to check our comments with ">>" beginning. Please fix your mail client instead. Or use a different one. > -----Original Message----- > From: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> > Sent: Tuesday, November 14, 2023 10:11 PM > To: larry.lai <larry.lai@xxxxxxxxxxxxxxx> > Cc: lee@xxxxxxxxxx; linus.walleij@xxxxxxxxxx; pavel@xxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-gpio@xxxxxxxxxxxxxxx; linux-leds@xxxxxxxxxxxxxxx; GaryWang 汪之逸 <GaryWang@xxxxxxxxxxxx>; musa.lin@xxxxxxxxxxxxxxx; jack.chang@xxxxxxxxxxxxxxx; noah.hung@xxxxxxxxxxxxxxx > Subject: Re: [PATCH V7 1/3] mfd: Add support for UP board CPLD/FPGA No headers in the body please. > On Tue, Oct 31, 2023 at 09:51:17AM +0800, larry.lai wrote: > > The UP Squared board > > <http://www.upboard.com/> implements certain features (pin control, onboard LEDs or CEC) through an on-board CPLD/FPGA. > > > > This driver implements the line protocol to read and write registers > > from the FPGA through regmap. The register address map is also included. > > > > The UP Boards provide a few I/O pin headers (for both GPIO and > > functions), including a 40-pin Raspberry Pi compatible header. > > > > This patch implements support for the FPGA-based pin controller that > > s/This patch implements/Implement/ > > > manages direction and enable state for those header pins. > > > > Partial support UP boards: > > "for UP" or "supported" (choose one). > > > * UP core + CREX > > * UP core + CRST02 > > > Reported-by: kernel test robot <lkp@xxxxxxxxx> > > No, this tag can't be applied to the new code. > > > Signed-off-by: Gary Wang <garywang@xxxxxxxxxxxx> > > Signed-off-by: larry.lai <larry.lai@xxxxxxxxxxxxxxx> > > Missing Co-developed-by? > >> larry is our consultant for upstream This is confusing. More '>'s usually means deeper quotes. Your reply should be up against the left wall, like this one. > ... > > > +config MFD_INTEL_UPBOARD_FPGA > > I believe Intel has nothing to do with this one. The Intel SoC is accompanied with OEM FPGA, right? > >> we used Intel CPLD Altera MAX V/X for pin mux and provide more driving power for Raspberry Pi compatible HAT pins, will remove "INTEL" Please enable line-wrap. > > + tristate "Support for the Intel platform foundation kit UP board FPGA" > > Depends on the above this most likely to be updated. > >> ok If you agree with a comment, please trim it from your reply. [...] -- Lee Jones [李琼斯]
