On Tue, Jan 07, 2025 at 03:26:34PM +0000, Mark Brown wrote: > On Tue, Jan 07, 2025 at 03:13:24PM +0000, Will Deacon wrote: > > On Wed, Dec 11, 2024 at 01:02:50AM +0000, Mark Brown wrote: > > > > -Res0 27:0 > > > +UnsignedEnum 27 SF8MM8 > > > + 0b0 NI > > > + 0b1 IMP > > > +EndEnum > > > +UnsignedEnum 26 SF8MM4 > > > + 0b0 NI > > > + 0b1 IMP > > > +EndEnum > > > afaict, bits 27 and 26 are still RES0 in all the documentation I can > > find... > > They're in the 2024-09 XML release here: > > https://developer.arm.com/documentation/ddi0601/2024-09/AArch64-Registers/ID-AA64SMFR0-EL1--SME-Feature-ID-Register-0?lang=en > > which was current at the time the series was sent but I see that they've > been removed in the 2024-12 release which came out later, right at the > end of last year: > > https://developer.arm.com/documentation/ddi0601/2024-12/AArch64-Registers/ID-AA64SMFR0-EL1--SME-Feature-ID-Register-0?lang=en > > so we should just remove these. I'll respin (or should I do it > incrementally to save on re-review of the rest of it?). Gimme a sec as I'm the process of applying the other sysregs bits (which looked fine). Will
