On Sat, 05 Oct 2024 15:14:21 +0100, Mark Brown <broonie@xxxxxxxxxx> wrote: > > On Sat, Oct 05, 2024 at 01:36:09PM +0100, Marc Zyngier wrote: > > Mark Brown <broonie@xxxxxxxxxx> wrote: > > > > + // PSTATE.EXLOCK is set to 0 upon any exception to a higher > > > + // EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same > > > + // exception level. See ARM DDI 0487 RWTXBY, D.1.3.2 in K.a. > > > + if (kvm_has_gcs(vcpu->kvm) && > > > + (target_mode & PSR_EL_MASK) == (mode & PSR_EL_MASK)) { > > > + u64 gcscr = __vcpu_read_sys_reg(vcpu, GCSCR_EL1); > > > No, please. This only works by luck when a guest has AArch32 EL0, and > > creates more havoc on a NV guest. In general, this PSR_EL_MASK creates > > more problem than anything else, and doesn't fit the rest of the code. > > You say luck, I say careful architecture definition but sure. I wasn't talking about the architecture, but sure. > > > So this needs to: > > - explicitly only apply to exceptions from AArch64 > > - handle exception from EL2, since this helper already deals with that > > > The latter point of course means introducing GCSCR_EL2 (and everything > > that depends on it, such as the trap handling). > > For clarity, which trap handling specifically? All the traps described in the GCSCR_EL2 documentation -- I see two control bits described in K.a, all of which needs to be propagated and their effects handled. Similarly, GCSPR_EL2 needs to be defined. M. -- Without deviation from the norm, progress is not possible.