On 2024/9/27 20:20, Jason Gunthorpe wrote:
On Fri, Sep 27, 2024 at 08:12:20PM +0800, Yi Liu wrote:
Perhaps calling it a slice sounds more accurate, as I guess all
the confusion comes from the name "vIOMMU" that might be thought
to be a user space object/instance that likely holds all virtual
stuff like stage-1 HWPT or so?
yeah. Maybe this confusion partly comes when you start it with the
cache invalidation as well. I failed to get why a S2 hwpt needs to
be part of the vIOMMU obj at the first glance.
Both amd and arm have direct to VM queues for the iommu and these
queues have their DMA translated by the S2.
ok, this explains why the S2 should be part of the vIOMMU obj.
So their viommu HW concepts come along with a requirement that there
be a fixed translation for the VM, which we model by attaching a S2
HWPT to the VIOMMU object which get's linked into the IOMMU HW as
the translation for the queue memory.
Is the mapping of the S2 be static? or it an be unmapped per userspace?
--
Regards,
Yi Liu
