On Thu, Aug 22, 2024 at 04:44:12PM +0100, Catalin Marinas wrote:
> On Thu, Aug 22, 2024 at 02:15:21AM +0100, Mark Brown wrote:
> > +void do_el0_gcs(struct pt_regs *regs, unsigned long esr)
> > +{
> > + force_signal_inject(SIGSEGV, SEGV_CPERR, regs->pc, 0);
> > +}
> Just double checking: a GCSPOPM (for example, it can be a RET) from a
> non-GCS page would generate a classic permission fault with ISS2.GCS set
> rather than a GCS exception. That's my reading from the Arm ARM
> pseudocode, the text isn't clear to me.
Yes, we only generate GCS exceptions on checking values that have
successfully been loaded from memory or other GCS logic errors - memory
accesses generate data aborts.
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