On Wed, Apr 03, 2024 at 01:04:34AM -0700, Atish Patra wrote:
> SBI PMU Snapshot function optimizes the number of traps to
> higher privilege mode by leveraging a shared memory between the S/VS-mode
> and the M/HS mode. Add the definitions for that extension and new error
> codes.
>
> Reviewed-by: Anup Patel <anup@xxxxxxxxxxxxxx>
> Acked-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
> Signed-off-by: Atish Patra <atishp@xxxxxxxxxxxx>
> ---
> arch/riscv/include/asm/sbi.h | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 4afa2cd01bae..9aada4b9f7b5 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -132,6 +132,7 @@ enum sbi_ext_pmu_fid {
> SBI_EXT_PMU_COUNTER_STOP,
> SBI_EXT_PMU_COUNTER_FW_READ,
> SBI_EXT_PMU_COUNTER_FW_READ_HI,
> + SBI_EXT_PMU_SNAPSHOT_SET_SHMEM,
> };
>
> union sbi_pmu_ctr_info {
> @@ -148,6 +149,13 @@ union sbi_pmu_ctr_info {
> };
> };
>
> +/* Data structure to contain the pmu snapshot data */
> +struct riscv_pmu_snapshot_data {
> + u64 ctr_overflow_mask;
> + u64 ctr_values[64];
> + u64 reserved[447];
> +};
> +
> #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0)
> #define RISCV_PMU_RAW_EVENT_IDX 0x20000
>
> @@ -244,9 +252,11 @@ enum sbi_pmu_ctr_type {
>
> /* Flags defined for counter start function */
> #define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0)
> +#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1)
>
> /* Flags defined for counter stop function */
> #define SBI_PMU_STOP_FLAG_RESET BIT(0)
> +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1)
>
> enum sbi_ext_dbcn_fid {
> SBI_EXT_DBCN_CONSOLE_WRITE = 0,
> @@ -285,6 +295,7 @@ struct sbi_sta_struct {
> #define SBI_ERR_ALREADY_AVAILABLE -6
> #define SBI_ERR_ALREADY_STARTED -7
> #define SBI_ERR_ALREADY_STOPPED -8
> +#define SBI_ERR_NO_SHMEM -9
>
> extern unsigned long sbi_spec_version;
> struct sbiret {
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>
