On Fri, Jan 19, 2024 at 10:05 AM Meng Li <li.meng@xxxxxxx> wrote: > > Hi all: > > The core frequency is subjected to the process variation in semiconductors. > Not all cores are able to reach the maximum frequency respecting the > infrastructure limits. Consequently, AMD has redefined the concept of > maximum frequency of a part. This means that a fraction of cores can reach > maximum frequency. To find the best process scheduling policy for a given > scenario, OS needs to know the core ordering informed by the platform through > highest performance capability register of the CPPC interface. > > Earlier implementations of amd-pstate preferred core only support a static > core ranking and targeted performance. Now it has the ability to dynamically > change the preferred core based on the workload and platform conditions and > accounting for thermals and aging. > > Amd-pstate driver utilizes the functions and data structures provided by > the ITMT architecture to enable the scheduler to favor scheduling on cores > which can be get a higher frequency with lower voltage. > We call it amd-pstate preferred core. > > Here sched_set_itmt_core_prio() is called to set priorities and > sched_set_itmt_support() is called to enable ITMT feature. > Amd-pstate driver uses the highest performance value to indicate > the priority of CPU. The higher value has a higher priority. > > Amd-pstate driver will provide an initial core ordering at boot time. > It relies on the CPPC interface to communicate the core ranking to the > operating system and scheduler to make sure that OS is choosing the cores > with highest performance firstly for scheduling the process. When amd-pstate > driver receives a message with the highest performance change, it will > update the core ranking. Hi Boris, You've had comments on the previous version of this. Have they all been addressed?
