> From: Liu, Yi L <yi.l.liu@xxxxxxxxx> > Sent: Thursday, September 21, 2023 3:55 PM > > From: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx> > > When remapping hardware is configured by system software in scalable > mode > as Nested (PGTT=011b) and with PWSNP field Set in the PASID-table-entry, > it may Set Accessed bit and Dirty bit (and Extended Access bit if enabled) > in first-stage page-table entries even when second-stage mappings indicate > that corresponding first-stage page-table is Read-Only. > > As the result, contents of pages designated by VMM as Read-Only can be > modified by IOMMU via PML5E (PML4E for 4-level tables) access as part of > address translation process due to DMAs issued by Guest. > > This disallows read-only mappings in the domain that is supposed to be used > as nested parent. Reference from Sapphire Rapids Specification Update [1], > errata details, SPR17. Userspace should know this limitation by checking > the IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 flag reported in the > IOMMU_GET_HW_INFO > ioctl. > > [1] https://www.intel.com/content/www/us/en/content- > details/772415/content-details.html > > Signed-off-by: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx> > Signed-off-by: Yi Liu <yi.l.liu@xxxxxxxxx> Reviewed-by: Kevin Tian <kevin.tian@xxxxxxxxx>
