From: Jinrong Liang <cloudliang@xxxxxxxxxxx>
This commit adds a PEBS test that verifies all possible combinations
of PEBS-related bits in MSR_IA32_PERF_CAPABILITIES. This comprehensive
test ensures the accuracy of the PEBS feature.
Signed-off-by: Jinrong Liang <cloudliang@xxxxxxxxxxx>
---
.../selftests/kvm/x86_64/vmx_pmu_caps_test.c | 71 +++++++++++++++++++
1 file changed, 71 insertions(+)
diff --git a/tools/testing/selftests/kvm/x86_64/vmx_pmu_caps_test.c b/tools/testing/selftests/kvm/x86_64/vmx_pmu_caps_test.c
index 02903084598f..c1b1ba44bc26 100644
--- a/tools/testing/selftests/kvm/x86_64/vmx_pmu_caps_test.c
+++ b/tools/testing/selftests/kvm/x86_64/vmx_pmu_caps_test.c
@@ -21,6 +21,12 @@
#define MAX_LINEAR_ADDR_MASK GENMASK_ULL(15, 8)
#define ADDR_OFS_BIT 8
+#define PMU_CAP_LBR_FMT 0x3f
+#define PMU_CAP_SMM_FREEZE BIT_ULL(12)
+#define PMU_CAP_FW_WRITES BIT_ULL(13)
+#define PMU_CAP_PERF_METRICS_AVAILABLE BIT_ULL(PERF_CAP_METRICS_IDX)
+#define PMU_CAP_PEBS_OUTPUT_PT_AVAIL BIT_ULL(PERF_CAP_PT_IDX)
+#define PMU_CAP_PEBS_ALL (PERF_CAP_PEBS_MASK | PMU_CAP_PEBS_OUTPUT_PT_AVAIL)
union perf_capabilities {
struct {
@@ -331,6 +337,70 @@ static void test_ds_area_noncanonical_address(union perf_capabilities host_cap)
kvm_vm_free(vm);
}
+static void test_pebs_bit_combinations(union perf_capabilities host_cap)
+{
+ int ret;
+ uint64_t pebs_val, val;
+ struct kvm_vcpu *vcpu;
+ struct kvm_vm *vm = vm_create_with_one_vcpu(&vcpu, NULL);
+
+ TEST_REQUIRE(kvm_cpu_property(X86_PROPERTY_PMU_VERSION) > 1);
+ TEST_REQUIRE(host_cap.capabilities & PERF_CAP_PEBS_FORMAT);
+ TEST_REQUIRE(vcpu_get_msr(vcpu, MSR_IA32_MISC_ENABLE) &
+ MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL);
+
+ /*
+ * Test if PEBS_REC_FMT is set and the value is the same as host,
+ * the other PEBS bits are allowed to be set only if they are the
+ * same as host.
+ */
+ pebs_val = host_cap.capabilities & PMU_CAP_PEBS_ALL;
+
+ vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, pebs_val);
+ ASSERT_EQ(vcpu_get_msr(vcpu, MSR_IA32_PERF_CAPABILITIES),
+ (u64)pebs_val);
+
+ /* Test all PEBS bit combinations. */
+ for (val = 0x0; val <= (~0ul & PMU_CAP_PEBS_ALL); val++) {
+ /* Skips values that are not related to PEBS. */
+ if (val & (PMU_CAP_LBR_FMT | PMU_CAP_SMM_FREEZE |
+ PMU_CAP_FW_WRITES | PMU_CAP_PERF_METRICS_AVAILABLE))
+ continue;
+
+ /*
+ * Test that value of PEBS is rejected when the KVM doesn't
+ * supports Intel PT.
+ */
+ if ((val & PMU_CAP_PEBS_OUTPUT_PT_AVAIL) &&
+ (!(host_cap.capabilities & PMU_CAP_PEBS_OUTPUT_PT_AVAIL))) {
+ ret = _vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, val);
+ TEST_ASSERT(!ret, "Bad PEBS auxiliary bits = 0x%lx didn't fail", val);
+
+ continue;
+ }
+
+ /*
+ * Test that value of PEBS is rejected when carrying
+ * PEBS_REC_FMT if the value of PEBS is not equal to host.
+ */
+ if ((val & PERF_CAP_PEBS_FORMAT) && val != pebs_val) {
+ ret = _vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, val);
+ TEST_ASSERT(!ret, "Bad PEBS auxiliary bits = 0x%lx didn't fail", val);
+
+ continue;
+ }
+
+ /*
+ * Test that PEBS bits can be written simultaneously or
+ * independently if PEBS_REC_FMT is not carried.
+ */
+ vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, val);
+ ASSERT_EQ(vcpu_get_msr(vcpu, MSR_IA32_PERF_CAPABILITIES), val);
+ }
+
+ kvm_vm_free(vm);
+}
+
int main(int argc, char *argv[])
{
union perf_capabilities host_cap;
@@ -352,4 +422,5 @@ int main(int argc, char *argv[])
test_guest_wrmsr_perf_capabilities(host_cap);
test_lbr_perf_capabilities(host_cap);
test_ds_area_noncanonical_address(host_cap);
+ test_pebs_bit_combinations(host_cap);
}
--
2.31.1
