On Tue, Apr 19, 2022 at 12:22:08PM +0100, Mark Brown wrote: > This series provides initial support for the ARMv9 Scalable Matrix > Extension (SME). SME takes the approach used for vectors in SVE and > extends this to provide architectural support for matrix operations. A > more detailed overview can be found in [1]. Set CONFIG_ARM64_SME=n fixed a warning while running libhugetlbfs tests. /* * There are several places where we assume that the order value is sane * so bail out early if the request is out of bound. */ if (unlikely(order >= MAX_ORDER)) { WARN_ON_ONCE(!(gfp & __GFP_NOWARN)); return NULL; } WARNING: CPU: 122 PID: 4025 at mm/page_alloc.c:5383 __alloc_pages CPU: 122 PID: 4025 Comm: brk_near_huge Not tainted 5.18.0-rc5-next-20220503 #79 pstate: 20400009 (nzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : __alloc_pages lr : alloc_pages sp : ffff8000505470f0 x29: ffff8000505470f0 x28: ffff40028b3535c0 x27: 0000000000000000 x26: 1ffff0000a0a8ea2 x25: ffff800050547510 x24: 0000000000000dc0 x23: ffff921ddb818000 x22: 000000000000000e x21: 1ffff0000a0a8e28 x20: 0000000000040dc0 x19: ffffae1848c61ae0 x18: ffffae18357e7d24 x17: ffffae182fb75778 x16: 1fffe8005166a7d8 x15: 000000000000001a x14: 1fffe8005166a7cb x13: 0000000000000004 x12: ffff70000a0a8e03 x11: 1ffff0000a0a8e02 x10: 00000000f204f1f1 x9 : 000000000000f204 x8 : dfff800000000000 x7 : 00000000f3000000 x6 : 00000000f3f3f3f3 x5 : ffff70000a0a8e28 x4 : ffff40028b3535c0 x3 : 0000000000000000 x2 : 0000000000000001 x1 : 0000000000000001 x0 : 0000000000040dc0 Call trace: __alloc_pages alloc_pages kmalloc_order kmalloc_order_trace __kmalloc __regset_get regset_get_alloc fill_thread_core_info fill_note_info elf_core_dump do_coredump get_signal do_signal do_notify_resume el0_svc el0t_64_sync_handler el0t_64_sync irq event stamp: 28066 hardirqs last enabled at (28065): _raw_spin_unlock_irqrestore hardirqs last disabled at (28066): el1_dbg softirqs last enabled at (27438): fpsimd_preserve_current_state softirqs last disabled at (27436): fpsimd_preserve_current_state