Re: [RFC PATCH 11/13] x86/uintr: Introduce uintr_wait() syscall

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On 10/1/2021 2:29 PM, Thomas Gleixner wrote:
So we'd end up with two XSAVES on context switch. We can simply do:
         XSAVES();
         fpu.state.xtsate.uintr.uinv = 0;


I am a bit confused. Do we need to set UINV to 0 explicitly?

If XSAVES gets called twice during context switch then the UINV in the XSTATE buffer automatically gets set to 0. Since XSAVES saves the current UINV value in the MISC_MSR which was already set to 0 by the previous XSAVES.

Though, this probably happens due to pure luck than intentional design :)

which allows to do as many XRSTORS in a row as we want. Only the final
one on the way to user space will have to restore the real vector if the
register state is not valid:

        if (fpu_state_valid()) {
             if (needs_uinv(current)
                wrmsrl(UINV, vector);
        } else {
             if (needs_uinv(current)
                fpu.state.xtsate.uintr.uinv = vector;
             XRSTORS();
        }

I might have missed some subtle difference. Has this logic changed from what you previously suggested for arch_exit_to_user_mode_prepare()?

       if (xrstors_pending)) {
            // Update the saved xstate for xrstors
            // Unconditionally update the UINV since it could have been overwritten by calling XSAVES twice.
               current->xstate.uintr.uinv = UINTR_NOTIFICATION_VECTOR;
                current->xstate.uintr.uirr |= pir;
        } else {
                // Manually restore UIRR and UINV
                rdmsrl(IA32_UINTR_RR, uirr);
                wrmsrl(IA32_UINTR_RR, uirr | pir);

            misc.val64 = 0;
                misc.uittsz = current->uintr->uittsz;
                misc.uinv = UINTR_NOTIFICATION_VECTOR;
                wrmsrl(IA32_UINTR_MISC, misc.val64);
        }

Hmm?


The one case I can see this failing is if there was another XRSTORS after the "final" restore in arch_exit_to_user_mode_prepare()? I think that is not possible but I am not an expert on this. Did I misunderstand something?

Thanks,
Sohil




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