> As you said, pin -> ref mapping is board specific, so the API should > not assume knowledge of routing between Port and ECC. That information will probably end up in device tree. And X different implementations of ACPI, unless somebody puts there foot down and stops the snow flakes. > Imagine a system with two cascaded switch ASICs and a bunch of PHYs. > How do you express that by pure extensions to the proposed API? Device tree is good at that. ACPI might eventually catch up. How complex a setup do we actually expect? Can there be multiple disjoint SyncE trees within an Ethernet switch cluster? Or would it be reasonable to say all you need to configure is the clock source, and all other ports of the switches are slaves if SyncE is enabled for the port? I've never see any SOHO switch hardware which allows you to have disjoint PTP trees, so it does not sound too unreasonable to only allow a single SyncE tree per switch cluster. Also, if you are cascading switches, you generally don't put PHYs in the middle, you just connect the SERDES lanes together. Andrew
