On Mon, Aug 16, 2021 at 06:07:10PM +0200, Arkadiusz Kubalewski wrote: > The second part can be used to select the port from which the clock > gets recovered. Each PHY chip can have multiple pins on which the > recovered clock can be propagated. For example, a SyncE-capable PHY > can recover the carrier frequency of the first port, divide it > internally, and output it as a reference clock on PIN 0. This really sounds like its own thing, and not a PHC at all. > Next steps: > - Add CONFIG_SYNCE definition into Kconfig > - Add more configuration interfaces. Aiming at devlink, since this > would be device-wide configuration As a first step, finding an appropriate kernel/user space API would be needed. Thanks, Richard
