Hi Sean, I love your patch! Yet something to improve: [auto build test ERROR on tip/auto-latest] [also build test ERROR on next-20191129] [cannot apply to tip/x86/core kvm/linux-next v5.4] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Sean-Christopherson/x86-cpu-Clean-up-handling-of-VMX-features/20191128-094556 base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git e445033e58108a9891abfbc0dea90b066a75e4a9 config: x86_64-randconfig-s0-20191128 (attached as .config) compiler: gcc-7 (Debian 7.4.0-14) 7.4.0 reproduce: # save the attached .config to linux build tree make ARCH=x86_64 If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp@xxxxxxxxx> All errors (new ones prefixed by >>): In file included from arch/x86/include/asm/processor.h:22:0, from arch/x86/include/asm/cpufeature.h:5, from arch/x86/include/asm/thread_info.h:53, from include/linux/thread_info.h:38, from arch/x86/include/asm/preempt.h:7, from include/linux/preempt.h:78, from include/linux/percpu.h:6, from include/linux/cpuidle.h:14, from drivers/idle/intel_idle.c:45: drivers/idle/intel_idle.c: In function 'sklh_idle_state_table_update': >> drivers/idle/intel_idle.c:1287:10: error: 'MSR_IA32_FEATURE_CONTROL' undeclared (first use in this function); did you mean 'MSR_MISC_FEATURE_CONTROL'? rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); ^ arch/x86/include/asm/msr.h:279:28: note: in definition of macro 'rdmsrl' ((val) = native_read_msr((msr))) ^~~ drivers/idle/intel_idle.c:1287:10: note: each undeclared identifier is reported only once for each function it appears in rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); ^ arch/x86/include/asm/msr.h:279:28: note: in definition of macro 'rdmsrl' ((val) = native_read_msr((msr))) ^~~ vim +1287 drivers/idle/intel_idle.c 5dcef694860100 Len Brown 2016-04-06 1189 5dcef694860100 Len Brown 2016-04-06 1190 /* 5dcef694860100 Len Brown 2016-04-06 1191 * Translate IRTL (Interrupt Response Time Limit) MSR to usec 5dcef694860100 Len Brown 2016-04-06 1192 */ 5dcef694860100 Len Brown 2016-04-06 1193 5dcef694860100 Len Brown 2016-04-06 1194 static unsigned int irtl_ns_units[] = { 5dcef694860100 Len Brown 2016-04-06 1195 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 5dcef694860100 Len Brown 2016-04-06 1196 5dcef694860100 Len Brown 2016-04-06 1197 static unsigned long long irtl_2_usec(unsigned long long irtl) 5dcef694860100 Len Brown 2016-04-06 1198 { 5dcef694860100 Len Brown 2016-04-06 1199 unsigned long long ns; 5dcef694860100 Len Brown 2016-04-06 1200 3451ab3ebf92b1 Jan Beulich 2016-06-27 1201 if (!irtl) 3451ab3ebf92b1 Jan Beulich 2016-06-27 1202 return 0; 3451ab3ebf92b1 Jan Beulich 2016-06-27 1203 bef450962597ff Jan Beulich 2016-06-27 1204 ns = irtl_ns_units[(irtl >> 10) & 0x7]; 5dcef694860100 Len Brown 2016-04-06 1205 5dcef694860100 Len Brown 2016-04-06 1206 return div64_u64((irtl & 0x3FF) * ns, 1000); 5dcef694860100 Len Brown 2016-04-06 1207 } 5dcef694860100 Len Brown 2016-04-06 1208 /* 5dcef694860100 Len Brown 2016-04-06 1209 * bxt_idle_state_table_update(void) 5dcef694860100 Len Brown 2016-04-06 1210 * 5dcef694860100 Len Brown 2016-04-06 1211 * On BXT, we trust the IRTL to show the definitive maximum latency 5dcef694860100 Len Brown 2016-04-06 1212 * We use the same value for target_residency. 5dcef694860100 Len Brown 2016-04-06 1213 */ 5dcef694860100 Len Brown 2016-04-06 1214 static void bxt_idle_state_table_update(void) 5dcef694860100 Len Brown 2016-04-06 1215 { 5dcef694860100 Len Brown 2016-04-06 1216 unsigned long long msr; 3451ab3ebf92b1 Jan Beulich 2016-06-27 1217 unsigned int usec; 5dcef694860100 Len Brown 2016-04-06 1218 5dcef694860100 Len Brown 2016-04-06 1219 rdmsrl(MSR_PKGC6_IRTL, msr); 3451ab3ebf92b1 Jan Beulich 2016-06-27 1220 usec = irtl_2_usec(msr); 3451ab3ebf92b1 Jan Beulich 2016-06-27 1221 if (usec) { 5dcef694860100 Len Brown 2016-04-06 1222 bxt_cstates[2].exit_latency = usec; 5dcef694860100 Len Brown 2016-04-06 1223 bxt_cstates[2].target_residency = usec; 5dcef694860100 Len Brown 2016-04-06 1224 } 5dcef694860100 Len Brown 2016-04-06 1225 5dcef694860100 Len Brown 2016-04-06 1226 rdmsrl(MSR_PKGC7_IRTL, msr); 3451ab3ebf92b1 Jan Beulich 2016-06-27 1227 usec = irtl_2_usec(msr); 3451ab3ebf92b1 Jan Beulich 2016-06-27 1228 if (usec) { 5dcef694860100 Len Brown 2016-04-06 1229 bxt_cstates[3].exit_latency = usec; 5dcef694860100 Len Brown 2016-04-06 1230 bxt_cstates[3].target_residency = usec; 5dcef694860100 Len Brown 2016-04-06 1231 } 5dcef694860100 Len Brown 2016-04-06 1232 5dcef694860100 Len Brown 2016-04-06 1233 rdmsrl(MSR_PKGC8_IRTL, msr); 3451ab3ebf92b1 Jan Beulich 2016-06-27 1234 usec = irtl_2_usec(msr); 3451ab3ebf92b1 Jan Beulich 2016-06-27 1235 if (usec) { 5dcef694860100 Len Brown 2016-04-06 1236 bxt_cstates[4].exit_latency = usec; 5dcef694860100 Len Brown 2016-04-06 1237 bxt_cstates[4].target_residency = usec; 5dcef694860100 Len Brown 2016-04-06 1238 } 5dcef694860100 Len Brown 2016-04-06 1239 5dcef694860100 Len Brown 2016-04-06 1240 rdmsrl(MSR_PKGC9_IRTL, msr); 3451ab3ebf92b1 Jan Beulich 2016-06-27 1241 usec = irtl_2_usec(msr); 3451ab3ebf92b1 Jan Beulich 2016-06-27 1242 if (usec) { 5dcef694860100 Len Brown 2016-04-06 1243 bxt_cstates[5].exit_latency = usec; 5dcef694860100 Len Brown 2016-04-06 1244 bxt_cstates[5].target_residency = usec; 5dcef694860100 Len Brown 2016-04-06 1245 } 5dcef694860100 Len Brown 2016-04-06 1246 5dcef694860100 Len Brown 2016-04-06 1247 rdmsrl(MSR_PKGC10_IRTL, msr); 3451ab3ebf92b1 Jan Beulich 2016-06-27 1248 usec = irtl_2_usec(msr); 3451ab3ebf92b1 Jan Beulich 2016-06-27 1249 if (usec) { 5dcef694860100 Len Brown 2016-04-06 1250 bxt_cstates[6].exit_latency = usec; 5dcef694860100 Len Brown 2016-04-06 1251 bxt_cstates[6].target_residency = usec; 5dcef694860100 Len Brown 2016-04-06 1252 } 5dcef694860100 Len Brown 2016-04-06 1253 5dcef694860100 Len Brown 2016-04-06 1254 } d70e28f57e14a4 Len Brown 2016-03-13 1255 /* d70e28f57e14a4 Len Brown 2016-03-13 1256 * sklh_idle_state_table_update(void) d70e28f57e14a4 Len Brown 2016-03-13 1257 * d70e28f57e14a4 Len Brown 2016-03-13 1258 * On SKL-H (model 0x5e) disable C8 and C9 if: d70e28f57e14a4 Len Brown 2016-03-13 1259 * C10 is enabled and SGX disabled d70e28f57e14a4 Len Brown 2016-03-13 1260 */ d70e28f57e14a4 Len Brown 2016-03-13 1261 static void sklh_idle_state_table_update(void) d70e28f57e14a4 Len Brown 2016-03-13 1262 { d70e28f57e14a4 Len Brown 2016-03-13 1263 unsigned long long msr; d70e28f57e14a4 Len Brown 2016-03-13 1264 unsigned int eax, ebx, ecx, edx; d70e28f57e14a4 Len Brown 2016-03-13 1265 d70e28f57e14a4 Len Brown 2016-03-13 1266 d70e28f57e14a4 Len Brown 2016-03-13 1267 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */ d70e28f57e14a4 Len Brown 2016-03-13 1268 if (max_cstate <= 7) d70e28f57e14a4 Len Brown 2016-03-13 1269 return; d70e28f57e14a4 Len Brown 2016-03-13 1270 d70e28f57e14a4 Len Brown 2016-03-13 1271 /* if PC10 not present in CPUID.MWAIT.EDX */ d70e28f57e14a4 Len Brown 2016-03-13 1272 if ((mwait_substates & (0xF << 28)) == 0) d70e28f57e14a4 Len Brown 2016-03-13 1273 return; d70e28f57e14a4 Len Brown 2016-03-13 1274 6cfb2374f83bc7 Len Brown 2017-01-07 1275 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr); d70e28f57e14a4 Len Brown 2016-03-13 1276 d70e28f57e14a4 Len Brown 2016-03-13 1277 /* PC10 is not enabled in PKG C-state limit */ d70e28f57e14a4 Len Brown 2016-03-13 1278 if ((msr & 0xF) != 8) d70e28f57e14a4 Len Brown 2016-03-13 1279 return; d70e28f57e14a4 Len Brown 2016-03-13 1280 d70e28f57e14a4 Len Brown 2016-03-13 1281 ecx = 0; d70e28f57e14a4 Len Brown 2016-03-13 1282 cpuid(7, &eax, &ebx, &ecx, &edx); d70e28f57e14a4 Len Brown 2016-03-13 1283 d70e28f57e14a4 Len Brown 2016-03-13 1284 /* if SGX is present */ d70e28f57e14a4 Len Brown 2016-03-13 1285 if (ebx & (1 << 2)) { d70e28f57e14a4 Len Brown 2016-03-13 1286 d70e28f57e14a4 Len Brown 2016-03-13 @1287 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); d70e28f57e14a4 Len Brown 2016-03-13 1288 d70e28f57e14a4 Len Brown 2016-03-13 1289 /* if SGX is enabled */ d70e28f57e14a4 Len Brown 2016-03-13 1290 if (msr & (1 << 18)) 0138d8f0755b5b Len Brown 2014-04-04 1291 return; 0138d8f0755b5b Len Brown 2014-04-04 1292 } 0138d8f0755b5b Len Brown 2014-04-04 1293 d70e28f57e14a4 Len Brown 2016-03-13 1294 skl_cstates[5].disabled = 1; /* C8-SKL */ d70e28f57e14a4 Len Brown 2016-03-13 1295 skl_cstates[6].disabled = 1; /* C9-SKL */ d70e28f57e14a4 Len Brown 2016-03-13 1296 } d70e28f57e14a4 Len Brown 2016-03-13 1297 /* d70e28f57e14a4 Len Brown 2016-03-13 1298 * intel_idle_state_table_update() d70e28f57e14a4 Len Brown 2016-03-13 1299 * d70e28f57e14a4 Len Brown 2016-03-13 1300 * Update the default state_table for this CPU-id d70e28f57e14a4 Len Brown 2016-03-13 1301 */ d70e28f57e14a4 Len Brown 2016-03-13 1302 :::::: The code at line 1287 was first introduced by commit :::::: d70e28f57e14a481977436695b0c9ba165472431 intel_idle: prevent SKL-H boot failure when C8+C9+C10 enabled :::::: TO: Len Brown <len.brown@xxxxxxxxx> :::::: CC: Len Brown <len.brown@xxxxxxxxx> --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx Intel Corporation
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