On Tue, Nov 08, 2016 at 10:39:54AM -0800, Kyle Huey wrote: > Intel supports faulting on the CPUID instruction beginning with Ivy Bridge. > When enabled, the processor will fault on attempts to execute the CPUID > instruction with CPL>0. This will allow a ptracer to emulate the CPUID > instruction. > > Bit 31 of MSR_PLATFORM_INFO advertises support for this feature. It is > documented in detail in Section 2.3.2 of > http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/virtualization-technology-flexmigration-application-note.pdf > > Detect support for this feature and expose it as X86_FEATURE_CPUID_FAULT. > > Signed-off-by: Kyle Huey <khuey@xxxxxxxxxxxx> > Reviewed-by: Andy Lutomirski <luto@xxxxxxxxxx> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/include/asm/msr-index.h | 2 ++ > arch/x86/kernel/cpu/scattered.c | 22 +++++++++++++++++++++- > 3 files changed, 24 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index a396292..62962e8 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -184,16 +184,17 @@ > * Auxiliary flags: Linux defined - For features scattered in various > * CPUID levels like 0x6, 0xA etc, word 7. > * > * Reuse free bits when adding new feature flags! > */ > > #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ > #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ > +#define X86_FEATURE_CPUID_FAULT ( 7*32+ 4) /* Intel CPUID faulting */ Bit 0 in that leaf is free. Also, bit 4 is already claimed by RDT/CAT/... whatever that thing is going to be called so please do: #define X86_FEATURE_CPUID_FAULT ( 7*32+ 0) /* Intel CPUID faulting */ > > #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ > #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ > > #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ > #define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */ > #define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */ ... > for (cb = cpuid_bits; cb->feature; cb++) { > > /* Verify that the level is valid */ > max_level = cpuid_eax(cb->level & 0xffff0000); > if (max_level < cb->level || > max_level > (cb->level | 0xffff)) > continue; > > cpuid_count(cb->level, cb->sub_leaf, ®s[CR_EAX], > ®s[CR_EBX], ®s[CR_ECX], ®s[CR_EDX]); > > if (regs[cb->reg] & (1 << cb->bit)) > set_cpu_cap(c, cb->feature); > } > + > + for (mb = msr_bits; mb->feature; mb++) { > + if (rdmsrl_safe(mb->msr, &msrval)) > + continue; <--- newline here. > + if (msrval & (1ULL << mb->bit)) if (msrval & BIT_ULL(mb->bit)) > + set_cpu_cap(c, mb->feature); > + } > } > -- -- Regards/Gruss, Boris. SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) -- -- To unsubscribe from this list: send the line "unsubscribe linux-kselftest" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
