Le 14/05/2023 à 19:10, Ondřej Jirman a écrit :
On Sun, May 14, 2023 at 07:00:34PM +0200, Christophe JAILLET wrote:
Le 14/05/2023 à 17:35, Ondřej Jirman a écrit :
Hello Christophe,
[...]
This changes the recommeded order of reset release/clock enable steps, eg. A64
manual says:
3.3.6.4. Gating and reset
Make sure that the reset signal has been released before the release of
module clock gating;
Ok, so moving reset_control_deassert() (and my proposed
^^^^^^^^^^^^^^^^^^^^^^
devm_add_action_or_reset()) just after devm_reset_control_get() should keep
the expected order, right?
That would be after reset_control_deassert(). devm_reset_control_get() is just
resource management, like devm_clk_get().
Not sure to get your point. I think you misunderstood what I tried to say.
I propose to move reset_control_deassert() in a v2. And have
devm_add_action_or_reset() just after it.
Something like:
if (tmdev->chip->has_bus_clk_reset) {
tmdev->reset = devm_reset_control_get(dev, NULL);
if (IS_ERR(tmdev->reset))
return PTR_ERR(tmdev->reset);
ret = reset_control_deassert(tmdev->reset);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, sun8i_ths_reset_control_assert,
tmdev->reset);
if (ret)
return ret;
tmdev->bus_clk = devm_clk_get_enabled(&pdev->dev, "bus");
if (IS_ERR(tmdev->bus_clk))
return PTR_ERR(tmdev->bus_clk);
}
if (tmdev->chip->has_mod_clk) {
tmdev->mod_clk = devm_clk_get_enabled(&pdev->dev, "mod");
if (IS_ERR(tmdev->mod_clk))
return PTR_ERR(tmdev->mod_clk);
}
ret = clk_set_rate(tmdev->mod_clk, 24000000);
if (ret)
return ret;
This would keep the order of operation, still fix the leak in the probe
and still save some LoC.
Would it make it?
CJ
regards,
o.
