+Manish On Wed, Nov 16, 2022, Lukas Bulwahn wrote: > A request to Manish Narani (see Link) asked for clarification of the > reference to the config ARCH_VERSAL in the support of Xilinx SoCs with > DesignWare Core USB3 IP. > > As there is no response, clean up the reference to the non-existing config > symbol. While at it, follow up on Felipe Balbi's request to add the > alternative COMPILE_TEST dependency. > > Link: https://urldefense.com/v3/__https://lore.kernel.org/all/CAKXUXMwgWfX8*OvY0aCwRNukencwJERAZzU7p4eOLXQ2zv6rAg@xxxxxxxxxxxxxx/__;Kw!!A4F2R9G_pg!aKs4dY02i_8ddqApoGvxFloscTBQxWlkhYT8XAyNkJjQWhTQGaD2-41qgo4BeUZVdK1Wc4lqSC-hp0mEiB1wyqcE3_U7$ > > Signed-off-by: Lukas Bulwahn <lukas.bulwahn@xxxxxxxxx> > --- > drivers/usb/dwc3/Kconfig | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig > index 03ededa86da1..b2f72b0e75c6 100644 > --- a/drivers/usb/dwc3/Kconfig > +++ b/drivers/usb/dwc3/Kconfig > @@ -152,11 +152,11 @@ config USB_DWC3_IMX8MP > > config USB_DWC3_XILINX > tristate "Xilinx Platforms" > - depends on (ARCH_ZYNQMP || ARCH_VERSAL) && OF > + depends on (ARCH_ZYNQMP || COMPILE_TEST) && OF > default USB_DWC3 > help > Support Xilinx SoCs with DesignWare Core USB3 IP. > - This driver handles both ZynqMP and Versal SoC operations. > + This driver handles ZynqMP SoC operations. > Say 'Y' or 'M' if you have one such device. > > config USB_DWC3_AM62 > -- > 2.17.1 > Acked-by: Thinh Nguyen <Thinh.Nguyen@xxxxxxxxxxxx> BR, Thinh
