> From: Jeffery Miller <jefferymiller@xxxxxxxxxx> > Sent: Friday, May 12, 2023 12:37 > To: Dmitry Torokhov <dmitry.torokhov@xxxxxxxxx> > Cc: Andrew Duggan <andrew@xxxxxxxxx>; Jonathan Denose > <jdenose@xxxxxxxxxxxx>; jdenose@xxxxxxxxxx; Lyude Paul > <lyude@xxxxxxxxxx>; loic.poulain@xxxxxxxxxx; > benjamin.tissoires@xxxxxxxxxx; Andrew Duggan > <aduggan@xxxxxxxxxxxxx>; Jonathan Cameron > <Jonathan.Cameron@xxxxxxxxxx>; Maximilian Luz > <luzmaximilian@xxxxxxxxx>; Miguel Ojeda <ojeda@xxxxxxxxxx>; Uwe Kleine- > König <u.kleine-koenig@xxxxxxxxxxxxxx>; linux-input@xxxxxxxxxxxxxxx; > linux-kernel@xxxxxxxxxxxxxxx > Subject: Re: [PATCH] Input: synaptics-rmi4 - retry reading SMBus version on > resume > > CAUTION: Email originated externally, do not click links or open attachments > unless you recognize the sender and know the content is safe. > > > On Wed, May 10, 2023 at 3:06 PM Dmitry Torokhov > <dmitry.torokhov@xxxxxxxxx> wrote: > > > > > > I am not really fond of adding random repeats in the code base. > > Andrew, do you know if the Synaptics device needs certain delay when > > switching to SMbus mode? > > > That's reasonable. It's true this is a sleep to workaround rmi_smbus' > expectation that > it is able to successfully read from the i801 i2c smbus addr 0x2c on resume > when it cannot. > > I do not know why the i801 i2c addr 0x2c is not responding on resume. > Infrequently it won't respond on boot during the initial > psmouse_smbus_create_companion but that is less noticeable since it will > stay in ps/2 mode and just lack features. > > I do know adding a sleep in-between the psmouse deactivate call and > rmi_smbus's attempts to read from the 0x2c addr allow it to succeed on this > machine. I do not know the details as to why however. Our Windows driver does a 30 ms delay between sending the disable command and trying to communicate over SMBus. I don’t know specifically why this delay is needed, but this is how we handle this case. > > I can apply workarounds until the underlying issue can be identified and > properly resolved. > > I can apply patches and provide any sort of debugging or extra information > that might be useful to anyone familiar with these devices. > > The smbus controller in this particular machine is: > 00:1f.3 SMBus [0c05]: Intel Corporation 8 Series/C220 Series Chipset Family > SMBus Controller [8086:8c22] (rev 04) > > Perhaps there's some way to detect when the addr is available later and have > it trigger a new probe similar to how psmouse_smbus_notifier is triggered > when the i801 bus becomes available? > > Thank You, > Jeff Andrew
