Hi Jonathan, On Sun, Nov 27, 2022 at 02:41:07PM +0000, Jonathan Cameron wrote: > From: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx> > > This problem was discovered in IIO as a side effect of the discussions about > relaxing kmalloc alignment on arm64 and resulted in a series of large > patch sets. > > https://lore.kernel.org/linux-iio/20220508175712.647246-1-jic23@xxxxxxxxxx/ > > Unsurprisingly there are cases of it in other subsystems. > > The short version of this is that there are a few known arm64 chips where > ___cacheline_aligned enforces 64 byte alignment which is what we typically > want for performance optimization as the size of the L1 cache lines. > However, further out in the cache hierarchy we have caches with 128 byte > lines. Those are the ones that matter for DMA safety. > So we need the larger alignment guarantees of ARCH_KMALLOC_MINALIGN which > in this case is 128 bytes. I wonder if we could have something like ____dmasafe_aligned instead of sprinkling ARCH_KMALLOC_MINALIGN around? > > There is one other use of ____cacheline_aligned in input: > joystick/iforce/iforce-usb.c > > Whilst suspicious I'm not sure enough of the requirements of USB to > know if they are there for DMA safety or some other constraint. Yes, USB has requirements similar to SPI. Thanks. -- Dmitry
