From: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
On some architectures (e.g. arm64), ____cachline_aligned only aligns
to the cacheline size of the L1 cache size. L1_CACHE_BYTES in
arch64/include/asm/cache.h Unfortunately DMA safety on these
architectures requires the buffer no share a last level cache cacheline
given by ARCH_DMA_MINALIGN which has a greater granularity.
ARCH_DMA_MINALIGN is not defined for all architectures, but when it is
defined it is used to set the size of ARCH_KMALLOC_MINALIGN
to allow DMA safe buffer allocations.
As such the correct alignment requirement is
__aligned(ARCH_KMALLOC_MINALIGN).
This has recently been fixed in other subsystems such as IIO.
Fixes tag for this is complex as at the time of original introduction, it
is likely that there were no cases where the two alignments were different.
Fixes: 1dbe7dada2d0 ("Input: ads7846 - make transfer buffers DMA safe")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
Cc: Daniel Mack <daniel@xxxxxxxxxx>
---
drivers/input/touchscreen/ads7846.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c
index bed68a68f330..074ca9f59788 100644
--- a/drivers/input/touchscreen/ads7846.c
+++ b/drivers/input/touchscreen/ads7846.c
@@ -337,7 +337,7 @@ struct ser_req {
* DMA (thus cache coherency maintenance) requires the
* transfer buffers to live in their own cache lines.
*/
- __be16 sample ____cacheline_aligned;
+ __be16 sample __aligned(ARCH_KMALLOC_MINALIGN);
};
struct ads7845_ser_req {
@@ -348,7 +348,7 @@ struct ads7845_ser_req {
* DMA (thus cache coherency maintenance) requires the
* transfer buffers to live in their own cache lines.
*/
- u8 sample[3] ____cacheline_aligned;
+ u8 sample[3] __aligned(ARCH_KMALLOC_MINALIGN);
};
static int ads7846_read12_ser(struct device *dev, unsigned command)
--
2.38.1
