On 2017-08-17 11:09, Russell King - ARM Linux wrote:
On Fri, Aug 11, 2017 at 11:16:20AM +0200, Linus Walleij wrote:
writel() should be guaranteeing that the values hit the hardware,
wmb() is
spelled out "write memory barrier" I don't see what you're after here.
Incorrect. writel() has a barrier which ensures that data written to
memory (eg, dma coherent memory) is visible to the hardware prior to
the write hitting the hardware.
There is no barrier to ensure that the write hits the hardware in a
timely manner - the write can be buffered by the buses, which will
delay it before it hits its destination.
PCI particularly buffers MMIO writes, and the requirement there has
always been that if you need the write to hit the hardware in a timely
fashion, you must perform a read-back to force the bus to deliver the
write (since a read is not allowed to overlap a write.)
The solution is never to use barrier() - barrier() is a _compiler_
barrier and does nothing for posted writes on hardware buses.
Thanks for clarification. I thought I just need a wmb() to make sure
writel()
can not be reordered with another store operation. I wasn't aware that
writel()
is defined to guarantee this on every arch.
That having the correct execution order is not enough on some buses
because
of buffering is really something to be aware of, thanks again for
pointing
this out.
So for the scenario I was concerned about I would expect the irqchip
driver
guarantees the write actually hits the the hardware (if necessary read
it
back) before the function (disable_irq_nosync()) returns, is that
correct?
Though, having the need should be very unlikely.
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