On Tue, Oct 09, 2012 at 09:43:13AM +0200, Linus Walleij wrote: > On Sat, Oct 6, 2012 at 6:09 AM, Christopher Heiny <cheiny@xxxxxxxxxxxxx> wrote: > > + * @cs_assert - For systems where the SPI subsystem does not control the CS/SSB > > + * line, or where such control is broken, you can provide a custom routine to > > + * handle a GPIO as CS/SSB. This routine will be called at the beginning and > > + * end of each SPI transaction. The RMI SPI implementation will wait > > + * pre_delay_us after this routine returns before starting the SPI transfer; > > + * and post_delay_us after completion of the SPI transfer(s) before calling it > > + * with assert==FALSE. > Hm hm, can you describe the case where this happens? > Usually we don't avoid fixes for broken drivers by duct-taping > solutions into other drivers, instead we fix the SPI driver. > I can think of systems where CS is asserted not by using > GPIO but by poking some special register for example, which > is a valid reason for including this, but working around broken > SPI drivers is not a valid reason to include this. > (Paging Mark about it.) Yeah, this seems silly - by this logic we'd have to go round implementing manual /CS control in every single SPI client driver which isn't terribly sensible. The driver should just assume that the SPI controller does what it's told. As you say if there's an issue the relevant controller driver should take care of things. We should also have generic support in the SPI framework for GPIO based /CS, there's enough drivers open coding this already either due to hardware limitations or to support extra chip selects. The ability of SPI hardware and driver authors to get /CS right is pretty depressing :/ -- To unsubscribe from this list: send the line "unsubscribe linux-input" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
