On Tue, May 11, 2010 at 23:23, FUJITA Tomonori wrote: > Seems that kmalloc is not cacheline aligned on some architectures but > they works. Probably, we might be just lucky because in general they > allocate larger buffers than 64 for DMA via kmalloc and the buffers > are aligned on the size? i think the magic combo is: - DMA buffer is written to (receive) - some driver state is in the same cacheline as the DMA buffer - that driver state is used after the flush but before the DMA finishes - only on arches that need software cache coherency so i could see this not being an obvious issue for many people -mike -- To unsubscribe from this list: send the line "unsubscribe linux-input" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
