On Tue, May 11, 2010 at 16:46, Christoph Lameter wrote: > On Tue, 11 May 2010, Mike Frysinger wrote: >> > DMA. If the arch can only DMA into cacheline aligned objects then the >> > correct method is to force kmalloc alignment to cacheline size. >> >> these are SPI drivers and are usable on any arch that supports a SPI >> bus (which is pretty much every arch). forget about "embedded" >> arches. >> >> the issue here is simple: a SPI driver (AD7877) needs to do a receive >> SPI transfer into a DMA safe buffer. what is the exact API to >> dynamically allocate memory for the structure with this buffer >> embedded in it such that the start of the structure is cached aligned >> ? creating a dedicated kmem cache may work, but it isnt a scalable >> solution if every SPI driver needs to create its own cache. > > kmalloc returns a pointer to a DMA safe buffer. There is no requirement on > the x86 hardware that the DMA buffers have to be cache aligned. Cachelines > will be invalidated as needed. so this guarantee is made by the kmalloc() API ? and for arches where the cacheline invalidation is handled in software rather than hardware, they must declare a min alignment value for kmalloc to be at least as big as their cache alignment ? does the phrase "DMA safe buffer" imply cache alignment ? -mike -- To unsubscribe from this list: send the line "unsubscribe linux-input" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
