From: David Brownell <dbrownell@xxxxxxxxxxxxxxxxxxxxx>
We had a report a while back that the ads7846 driver had some issues
when used with DMA-based SPI controllers (like atmel_spi) on systems
where main memory is not DMA-coherent (most non-x86 boards) ... but no
mergeable patch addressed it. Pending any more comprehensive fix,
just push the relevant data into cache lines that won't be shared,
preventing those issues (but not in a very pretty way).
Signed-off-by: David Brownell <dbrownell@xxxxxxxxxxxxxxxxxxxxx>
---
Please merge for 2.6.27-final (and forward to -stable for backports);
this lack-of-patch has lingered for way too long.
drivers/input/touchscreen/ads7846.c | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
--- a/drivers/input/touchscreen/ads7846.c
+++ b/drivers/input/touchscreen/ads7846.c
@@ -85,10 +85,6 @@ struct ads7846 {
u16 x_plate_ohms;
u16 pressure_max;
- u8 read_x, read_y, read_z1, read_z2, pwrdown;
- u16 dummy; /* for the pwrdown read */
- struct ts_event tc;
-
struct spi_transfer xfer[18];
struct spi_message msg[5];
struct spi_message *last_msg;
@@ -116,6 +112,26 @@ struct ads7846 {
void *filter_data;
void (*filter_cleanup)(void *data);
int (*get_pendown_state)(void);
+
+ /* NOTE: this is a bit klugey. Ideally all these I/O buffers
+ * would be in a separate buffer (from the heap) to make DMA
+ * work better. Instead, we trust that starting them on their
+ * own cache line, at the end of this struct, suffices to avoid
+ * cacheline sharing issues -- pending any better fix.
+ *
+ * The first several systems to use this driver didn't use DMA
+ * with SPI, at least for small I/O requests as used here, so
+ * the cache line sharing issues wouldn't show up there.
+ */
+ u8 read_x ____cacheline_aligned;
+ u8 read_y;
+ u8 read_z1:
+ u8 read_z2;
+ u8 pwrdown;
+ u16 dummy; /* for the pwrdown read */
+
+ struct ts_event tc;
+
};
/* leave chip selected when we're done, for quicker re-select? */
--
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