On Wed, Dec 20, 2023 at 03:57:25PM +0100, Fabrice Gasnier wrote: > diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h > index ca35af30745f..9eb17481b07f 100644 > --- a/include/linux/mfd/stm32-timers.h > +++ b/include/linux/mfd/stm32-timers.h > @@ -41,6 +41,11 @@ > #define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ > #define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ > #define TIM_DIER_UIE BIT(0) /* Update interrupt */ > +#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */ > +#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */ > +#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */ > +#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */ > +#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */ > #define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */ > #define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */ > #define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */ > @@ -49,6 +54,7 @@ > #define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */ > #define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */ > #define TIM_SR_UIF BIT(0) /* Update interrupt flag */ > +#define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */ > #define TIM_EGR_UG BIT(0) /* Update Generation */ > #define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ > #define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ > @@ -60,16 +66,23 @@ > #define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */ > #define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */ > #define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */ > +#define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */ > +#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */ > +#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */ > +#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */ > #define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ > #define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ > #define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ > #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ > #define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ > #define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */ > +#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */ > #define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ > #define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */ > +#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */ > #define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ > #define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */ > +#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */ I forgot to mention that you should move the introduction of these defines to the subsequent patch adding support for capture events because that's where the defines are actually used. William Breathitt Gray
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