Hi, +Anand, On 23. 09. 20 22:47, Jonathan Cameron wrote: > On Tue, 22 Sep 2020 15:46:24 +0200 > Lars-Peter Clausen <lars@xxxxxxxxxx> wrote: > >> The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx >> 7 series FPGAs. The system-monitor is the equivalent to the XADC in the >> Xilinx UltraScale and UltraScale+ FPGAs. >> >> The IP designers did a good job at maintaining backwards compatibility and >> only minor changes are required to add basic support for the system-monitor >> core. >> >> The non backwards compatible changes are: >> * Register map offset was moved from 0x200 to 0x400 >> * Only one ADC compared to two in the XADC >> * 10 bit ADC instead of 12 bit ADC >> * Two of the channels monitor different supplies >> >> Add the necessary logic to accommodate these changes to support the >> system-monitor in the XADC driver. >> >> Note that this patch does not include support for some new features found >> in the system-monitor like additional alarms, user supply monitoring and >> secondary system-monitor access. This might be added at a later time. >> >> Signed-off-by: Lars-Peter Clausen <lars@xxxxxxxxxx> > > Very nice. Will let this sit on the mailing list a bit longer > but looks good to me. FYI: I have asked Anand to take a look at it and retest. Thanks, Michal
