Re: [PATCH 18/20] dt-bindings:iio:adc:amlogic,meson-saradc yaml conversion

[Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx>]

Hi Jonathan,

On Sat, Sep 5, 2020 at 7:32 PM Jonathan Cameron <jic23@xxxxxxxxxx> wrote:
>
> From: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
>
> This binding is non trivial due to the range of different parts
> supported having several subtle quirks.
thank you for working on this!

> I am far from sure I have these correct. For example:
> 1) Can we have the clock adc_sel without adc_clk?
adc_sel and adc_clk only exist on GXBB and newer
Meson8, Meson8b and Meson8m2 have these clocks built into the SAR ADC IP block

> 2) I haven't restricted the amlogic,hhi-sysctrl to only
>    be present on the relevant parts if nvmem stuff also is, but
>    it would seem to be rather odd if it were otherwise.
yes, I think we can restrict this later

[...]
> +        adc@9680 {
> +            compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
> +            #io-channel-cells = <1>;
> +            reg = <0x0 0x9680 0x0 0x34>;
> +            interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
> +            clocks = <&xtal>,
> +                <&clkc CLKID_SAR_ADC>,
> +                <&clkc CLKID_SAR_ADC_CLK>,
> +                <&clkc CLKID_SAR_ADC_SEL>;
> +            clock-names = "clkin", "core";
CLKID_SAR_ADC_CLK and CLKID_SAR_ADC_SEL should not be in this Meson8b example

I have attached a patch for this as well as for making the clock
selection more restrictive (to catch errors like this). feel free to
include it in your patch if you think that it improves things


Best regards,
Martin

diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
index 5b2e07828c3d..6d94bf76900e 100644
--- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
@@ -35,18 +35,9 @@ properties:
     description: Interrupt indicates end of sampling.
     maxItems: 1
 
-  clocks:
-    minItems: 2
-    maxItems: 4
-
-  clock-names:
-    items:
-      - const: clkin
-      - const: core
-      - const: adc_clk
-      - const: adc_sel
-    minItems: 2
-    maxItems: 4
+  clocks: true
+
+  clock-names: true
 
   vref-supply: true
 
@@ -79,10 +70,26 @@ allOf:
       properties:
         nvmem-cells: true
         nvmem-cell-names: true
+        clock-names:
+          items:
+            - const: clkin
+            - const: core
+          minItems: 2
+        clocks:
+          minItems: 2
     else:
       properties:
         nvmem-cells: false
         mvmem-cel-names: false
+        clock-names:
+          items:
+            - const: clkin
+            - const: core
+            - const: adc_clk
+            - const: adc_sel
+          minItems: 4
+        clocks:
+          minItems: 4
 
   - if:
       properties:
@@ -132,10 +139,7 @@ examples:
             #io-channel-cells = <1>;
             reg = <0x0 0x9680 0x0 0x34>;
             interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
-            clocks = <&xtal>,
-                <&clkc CLKID_SAR_ADC>,
-                <&clkc CLKID_SAR_ADC_CLK>,
-                <&clkc CLKID_SAR_ADC_SEL>;
+            clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
             clock-names = "clkin", "core";
             nvmem-cells = <&tsens_caldata>;
             nvmem-cell-names = "temperature_calib";