+
+ ret = regmap_read(data->regmap,
+ BMI088_ACCEL_REG_ACC_RANGE, &range);
+ if (ret < 0)
+ return ret;
+
+ ret = bmi088_accel_get_axis(data, chan, val);
+ if (ret < 0)
+ return ret;
+
+ *val = (*val * 3 * 980 * (0x01 << range)) >> 15;
+
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
[...]
+}
+
+static int bmi088_accel_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val, int val2, long mask)
+{
+ struct bmi088_accel_data *data = iio_priv(indio_dev);
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ mutex_lock(&data->mutex);
+ ret = bmi088_accel_set_bw(data, val, val2);
+ mutex_unlock(&data->mutex);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("12.5 25 50 100 200 400 800
1600");
+
+static struct attribute *bmi088_accel_attributes[] = {
+ &iio_const_attr_sampling_frequency_available.dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group bmi088_accel_attrs_group = {
+ .attrs = bmi088_accel_attributes,
+};
+
+#define BMI088_ACCEL_CHANNEL(_axis, bits) { \
+ .type = IIO_ACCEL, \
+ .modified = 1, \
+ .channel2 = IIO_MOD_##_axis, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
+ .scan_index = AXIS_##_axis, \
+ .scan_type = { \
+ .sign = 's', \
+ .realbits = (bits), \
+ .storagebits = 16, \
+ .shift = 16 - (bits), \
+ .endianness = IIO_LE, \
+ }, \
+}
+
+#define BMI088_ACCEL_CHANNELS(bits) { \
+ { \
+ .type = IIO_TEMP, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_OFFSET), \
+ .scan_index = -1, \
+ }, \
+ BMI088_ACCEL_CHANNEL(X, bits), \
+ BMI088_ACCEL_CHANNEL(Y, bits), \
+ BMI088_ACCEL_CHANNEL(Z, bits), \
+ IIO_CHAN_SOFT_TIMESTAMP(3), \
+}
+
+static const struct iio_chan_spec bmi088_accel_channels[] =
+ BMI088_ACCEL_CHANNELS(16);
+
+static const struct bmi088_accel_chip_info
bmi088_accel_chip_info_tbl[] = {
+ [0] = {
+ .name = "BMI088A",
+ .chip_id = 0x1E,
+ .channels = bmi088_accel_channels,
+ .num_channels = ARRAY_SIZE(bmi088_accel_channels),
+ .scale_table = { {9610, BMI088_ACCEL_RANGE_3G},
+ {19122, BMI088_ACCEL_RANGE_6G},
+ {38344, BMI088_ACCEL_RANGE_12G},
+ {76590, BMI088_ACCEL_RANGE_24G} },
+ },
+};
+
+static const struct iio_info bmi088_accel_info = {
+ .attrs = &bmi088_accel_attrs_group,
+ .read_raw = bmi088_accel_read_raw,
+ .write_raw = bmi088_accel_write_raw,
+};
+
+static const unsigned long bmi088_accel_scan_masks[] = {
+ BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
+ 0};
+
+
+
+#ifdef CONFIG_PM
+static int bmi088_accel_set_power_state(struct bmi088_accel_data *data,
+ bool on)
+{
+ struct device *dev = regmap_get_device(data->regmap);
+ int ret;
+
+ if (on) {
+ ret = pm_runtime_get_sync(dev);
+ } else {
+ pm_runtime_mark_last_busy(dev);
+ ret = pm_runtime_put_autosuspend(dev);
+ }
+
+ if (ret < 0) {
+ dev_err(dev, "Failed: %s(%d)\n", __func__, on);
+ if (on)
+ pm_runtime_put_noidle(dev);
+
+ return ret;
+ }
+
+ return 0;
+}
+#else
+static int bmi088_accel_set_power_state(struct bmi088_accel_data *data,
+ bool on)
+{
+ return 0;
+}
+#endif
+
+static int bmi088_accel_chip_init(struct bmi088_accel_data *data)
+{
+ struct device *dev = regmap_get_device(data->regmap);
+ int ret, i;
+ unsigned int val;
+
+ /* Do a dummy read (of chip ID), to enable SPI interface */
+ regmap_read(data->regmap, BMI088_ACCEL_REG_CHIP_ID, &val);
+
+ /*
+ * Reset chip to get it in a known good state. A delay of 1ms after
+ * reset is required according to the data sheet
+ */
+ regmap_write(data->regmap, BMI088_ACCEL_REG_RESET,
+ BMI088_ACCEL_RESET_VAL);
+ usleep_range(1000, 2000);
+
+ /* Do a dummy read (of chip ID), to enable SPI interface after
reset */
+ regmap_read(data->regmap, BMI088_ACCEL_REG_CHIP_ID, &val);
+
+ /* Read chip ID */
+ ret = regmap_read(data->regmap, BMI088_ACCEL_REG_CHIP_ID, &val);
+ if (ret < 0) {
+ dev_err(dev, "Error: Reading chip id\n");
+ return ret;
+ }
+
+ /* Validate chip ID */
+ dev_dbg(dev, "Chip Id %x\n", val);
+ for (i = 0; i < ARRAY_SIZE(bmi088_accel_chip_info_tbl); i++) {
+ if (bmi088_accel_chip_info_tbl[i].chip_id == val) {
+ data->chip_info = &bmi088_accel_chip_info_tbl[i];
+ break;
+ }
+ }
+
+ if (!data->chip_info) {
+ dev_err(dev, "Invalid chip %x\n", val);
+ return -ENODEV;
+ }
+
+ /* Set Active mode (and wait for 5ms) */
+ ret = bmi088_accel_set_mode(data, BMI088_ACCEL_MODE_ACTIVE);
+ if (ret < 0)
+ return ret;
+
+ usleep_range(5000, 10000);
+
+ /* Enable accelerometer */
+ ret = bmi088_accel_enable(data, true);
+ if (ret < 0)
+ return ret;
+
+ /* Set Bandwidth */
+ ret = bmi088_accel_set_bw(data, BMI088_ACCEL_MODE_ODR_100,
+ BMI088_ACCEL_MODE_OSR_NORMAL);
+ if (ret < 0)
+ return ret;
+
+ /* Set Default Range */
+ ret = regmap_write(data->regmap, BMI088_ACCEL_REG_ACC_RANGE,
+ BMI088_ACCEL_RANGE_6G);
+ if (ret < 0) {
+ dev_err(dev, "Error writing ACC_RANGE\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int bmi088_accel_core_probe(struct device *dev, struct regmap *regmap,
+ int irq, const char *name, bool block_supported)
+{
+ struct bmi088_accel_data *data;
+ struct iio_dev *indio_dev;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ data = iio_priv(indio_dev);
+ dev_set_drvdata(dev, indio_dev);
+
+ data->regmap = regmap;
+
+ ret = bmi088_accel_chip_init(data);
+ if (ret < 0)
+ return ret;
+
+ mutex_init(&data->mutex);
+
+ indio_dev->dev.parent = dev;
+ indio_dev->channels = data->chip_info->channels;
+ indio_dev->num_channels = data->chip_info->num_channels;
+ indio_dev->name = name ? name : data->chip_info->name;
