On 04/19/2016 12:18 PM, Gregor Boirie wrote:
> Triggered buffering memory accesses are not aligned on per channel
> storagebits boundaries. Fix this by reading each channel individually to
> ensure proper alignment.
> Note that this patch drops the earlier optimisation that packs multiple
> channels reading into a single data block transaction when their
> respective I2C register addresses are contiguous.
>
Both the 'before' and 'after' versions seem to be doing one bus
transaction for each active channel in the scan mask. The optimization
you're mentioning was dropped in an older patch:
iio: st_sensors: read each channel individually
At most it makes that optimization harder to restore, right?
--
Regards,
Leonard
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