Re: [PATCH] iio: adc: xilinx-xadc: Convert to raw spinlock

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On 5/14/2015 12:10 PM, Sebastian Andrzej Siewior wrote:

Do you have any cyclictest numbers how much the latency increases on
heavy iio usage? Traditionally the primary handler should be very quick
/ short.

Sebastian

With no other processes running, I got the following results after a couple of hours on one of our devices:

admin@Xander-roboRIO:~# cyclictest -S -m -p 98
# /dev/cpu_dma_latency set to 0us
policy: fifo: loadavg: 0.01 0.07 0.12 1/176 1473

T: 0 ( 1373) P:98 I:1000 C:6503872 Min:      9 Act:   13 Avg:   13 Max:      51
T: 1 ( 1374) P:98 I:1500 C:4335914 Min:      9 Act:   12 Avg:   13 Max:      49

With a VI reading all default handles (raw, offset, scale, sampling_frequency) in /sys/bus/iio/devices/iio:device0 constantly in a while loop, I got the following results after a couple hours on the same device:

admin@Xander-roboRIO:~# cyclictest -S -m -p 98
# /dev/cpu_dma_latency set to 0us
policy: fifo: loadavg: 6.93 7.30 7.47 3/182 1530

T: 0 ( 1487) P:98 I:1000 C:4497008 Min:     11 Act:   20 Avg:   21 Max:      69
T: 1 ( 1488) P:98 I:1500 C:2998005 Min:     11 Act:   20 Avg:   22 Max:      59

--
Xander Huff
Staff Software Engineer
National Instruments
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