On 7/11/24 17:11, Richard Zhu wrote:
> Clean up code by using PHY interface.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> ---
[...]
> static int imx8_sata_enable(struct ahci_host_priv *hpriv)
> {
> - u32 val, reg;
> - int i, ret;
> + u32 val;
> + int ret;
> struct imx_ahci_priv *imxpriv = hpriv->plat_data;
> struct device *dev = &imxpriv->ahci_pdev->dev;
>
> - /* configure the hsio for sata */
> - ret = clk_prepare_enable(imxpriv->phy_pclk0);
> - if (ret < 0) {
> - dev_err(dev, "can't enable phy_pclk0.\n");
> + /*
> + * Since "REXT" pin is only present for first lane of i.MX8QM
> + * PHY, it's calibration results will be stored, passed
s/it's/its
> + * through second lane PHY, and shared with all three lane PHYs.
s/through/through to the
> + *
> + * Initialize the first two lane PHYs here, although only the
> + * third lane PHY is used by SATA.
> + */
--
Damien Le Moal
Western Digital Research
