On Fri, Jan 19, 2024 at 05:06:21PM +0530, Radhey Shyam Pandey wrote: > As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO > controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed > DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and > Xilinx udc controller maintainership duties to Mubin and Radhey. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx> > --- > Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 3 ++- > .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 3 ++- > Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++- > Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 ++- > Documentation/devicetree/bindings/usb/microchip,usb5744.yaml | 3 ++- > Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 3 ++- > 6 files changed, 12 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > index b29ce598f9aa..9952e0ef7767 100644 > --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Ceva AHCI SATA Controller > > maintainers: > - - Piyush Mehta <piyush.mehta@xxxxxxx> > + - Mubin Sayyed <mubin.sayyed@xxxxxxx> > + - Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx> > > description: | > The Ceva SATA controller mostly conforms to the AHCI interface with some For ata: Acked-by: Niklas Cassel <cassel@xxxxxxxxxx>
