On Fri, Jan 19, 2024 at 12:36 PM Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx> wrote: > > As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO > controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed > DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and > Xilinx udc controller maintainership duties to Mubin and Radhey. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx> > --- [snip] > diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > index b1fd632718d4..bb93baa88879 100644 > --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml > @@ -12,7 +12,8 @@ description: > PS_MODE). Every pin can be configured as input/output. > > maintainers: > - - Piyush Mehta <piyush.mehta@xxxxxxx> > + - Mubin Sayyed <mubin.sayyed@xxxxxxx> > + - Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx> > > properties: > compatible: For GPIO: Acked-by: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxx> [snip]
