On 9/6/23 18:53, Szuying Chen wrote:
> Cleared PxIS and PxIE with error recovery when ISR handle interface fatal.
> Then a SDB FIS with ERR (set PxIS.TFES) is received
> before PxCMD.ST is set to 0.
> When error recovery was finish and PxCMD.ST is set to 1.
> The HBA can't issue any new commands.
> Because the PxIS.TFES bit is not cleared.
> To avoid this,
> we adds the function to clear pending interrupt before COMRESET.
> It follows the AHCI 1.3.1 - section 6.2.2.2 specification.
>
> Signed-off-by: Szuying Chen <Chloe_Chen@xxxxxxxxxxxxxx>
Fixes tag ?
> ---
> V1->V2: On suggestion by Damien to renamed helper function and modified
> ahci_port_init() to make use of the helper.
> V2->V3: On suggestion by Niklas to modify commit log and delete the
> extra describe.
>
> drivers/ata/libahci.c | 35 +++++++++++++++++++++++------------
> 1 file changed, 23 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
> index e2bacedf28ef..f1263364fa97 100644
> --- a/drivers/ata/libahci.c
> +++ b/drivers/ata/libahci.c
> @@ -1256,6 +1256,26 @@ static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
> return sprintf(buf, "%d\n", emp->blink_policy);
> }
>
> +static void ahci_port_clear_pending_irq(struct ata_port *ap)
> +{
> + struct ahci_host_priv *hpriv = ap->host->private_data;
> + void __iomem *port_mmio = ahci_port_base(ap);
> + u32 tmp;
> +
> + /* clear SError */
> + tmp = readl(port_mmio + PORT_SCR_ERR);
> + dev_dbg(ap->host->dev, "PORT_SCR_ERR 0x%x\n", tmp);
> + writel(tmp, port_mmio + PORT_SCR_ERR);
> +
> + /* clear port IRQ */
> + tmp = readl(port_mmio + PORT_IRQ_STAT);
> + dev_dbg(ap->host->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
> + if (tmp)
> + writel(tmp, port_mmio + PORT_IRQ_STAT);
> +
> + writel(1 << ap->port_no, hpriv->mmio + HOST_IRQ_STAT);
> +}
> +
> static void ahci_port_init(struct device *dev, struct ata_port *ap,
> int port_no, void __iomem *mmio,
> void __iomem *port_mmio)
> @@ -1270,18 +1290,7 @@ static void ahci_port_init(struct device *dev, struct ata_port *ap,
> if (rc)
> dev_warn(dev, "%s (%d)\n", emsg, rc);
>
> - /* clear SError */
> - tmp = readl(port_mmio + PORT_SCR_ERR);
> - dev_dbg(dev, "PORT_SCR_ERR 0x%x\n", tmp);
> - writel(tmp, port_mmio + PORT_SCR_ERR);
> -
> - /* clear port IRQ */
> - tmp = readl(port_mmio + PORT_IRQ_STAT);
> - dev_dbg(dev, "PORT_IRQ_STAT 0x%x\n", tmp);
> - if (tmp)
> - writel(tmp, port_mmio + PORT_IRQ_STAT);
> -
> - writel(1 << port_no, mmio + HOST_IRQ_STAT);
> + ahci_port_clear_pending_irq(ap);
>
> /* mark esata ports */
> tmp = readl(port_mmio + PORT_CMD);
> @@ -1603,6 +1612,8 @@ int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
> tf.status = ATA_BUSY;
> ata_tf_to_fis(&tf, 0, 0, d2h_fis);
>
> + ahci_port_clear_pending_irq(ap);
> +
> rc = sata_link_hardreset(link, timing, deadline, online,
> ahci_check_ready);
>
> --
> 2.39.2
>
--
Damien Le Moal
Western Digital Research
