Just like RK3568, the RK3588 has a DWC based AHCI controller.
Signed-off-by: Sebastian Reichel <sebastian.reichel@xxxxxxxxxxxxx>
---
FWIW IDK what exactly the ASIC clock is. The TRM does not provide any
details unfortunately. It is required for functional SATA, though.
---
.../devicetree/bindings/ata/snps,dwc-ahci-common.yaml | 6 ++++--
Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml | 6 ++++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml b/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml
index c1457910520b..0df8f49431eb 100644
--- a/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml
+++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml
@@ -31,11 +31,11 @@ properties:
PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
clock, etc.
minItems: 1
- maxItems: 4
+ maxItems: 5
clock-names:
minItems: 1
- maxItems: 4
+ maxItems: 5
items:
oneOf:
- description: Application APB/AHB/AXI BIU clock
@@ -50,6 +50,8 @@ properties:
const: rxoob
- description: SATA Ports reference clock
const: ref
+ - description: Rockchip ASIC clock
+ const: asic
resets:
description:
diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
index 5afa4b57ce20..c6a0d6c8b62c 100644
--- a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
+++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
@@ -23,9 +23,11 @@ properties:
const: snps,dwc-ahci
- description: SPEAr1340 AHCI SATA device
const: snps,spear-ahci
- - description: Rockhip RK3568 AHCI controller
+ - description: Rockhip AHCI controller
items:
- - const: rockchip,rk3568-dwc-ahci
+ - enum:
+ - rockchip,rk3568-dwc-ahci
+ - rockchip,rk3588-dwc-ahci
- const: snps,dwc-ahci
patternProperties:
--
2.39.2
