On 4/24/22 01:52, Arnd Bergmann wrote:
On Sun, Apr 24, 2022 at 4:09 AM Guenter Roeck <linux@xxxxxxxxxxxx> wrote:
On 4/23/22 12:55, Arnd Bergmann wrote:
On Sat, Apr 23, 2022 at 1:41 AM Guenter Roeck <linux@xxxxxxxxxxxx> wrote:
On Sat, Apr 23, 2022 at 12:04:31AM +0200, Arnd Bergmann wrote:
Odd, I can't reproduce this at all. Do you get any console output at
all for this?
Is this the plain omap1_defconfig, or something else?
No, it is my own sx1 specific configuration.
https://github.com/groeck/linux-build-test/blob/master/rootfs/arm/qemu_sx1_defconfig
I don't recall where I got it from but ...
Ok, that explains it, thanks!
I fixed all the defconfig files that come with the kernel, but for your own
ones you have to add
# CONFIG_ARCH_MULTI_V7 is not set
into the defconfig file, otherwise the multiplatform target defaults to
an ARMv7 instead of ARMv5 build. For an OMAP15xx as in the SX1,
you also need to enable CONFIG_ARCH_MULTI_V4T.
This is slightly unfortunate, but I don't see any way to avoid it, and the
modified defconfig will still work fine with older kernel trees.
Yes, that works. I changed it in my configuration.
One thing I keep having to apply myself is this snippet:
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 0bfad62ea858..87c695703580 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -441,7 +441,6 @@ __arm925_setup:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mov r0, #4 @ disable write-back
on caches explicitly
- mcr p15, 7, r0, c15, c0, 0
#endif
it does not have CONFIG_CPU_DCACHE_WRITETHROUGH enabled.
Maybe it was disabled explicitly for the sx1_defconfig because of this
bug. I would think that this is required for actual sx1 hardware because the
option is default-enabled for ARM925T, and that CPU core is exclusively
used in OMAP15xx.
That looks like a bug in qemu. ARM925T instruction support is limited to V4T
instructions. qemu doesn't have explicit 5T support. It is either V4T
or V5.
Guenter
