On 27/02/2022 19:28, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
>
> RK356x supports up to 3 sata controllers which were compatible with the
> existing snps,dwc-ahci binding.
>
> Signed-off-by: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
> ---
> changes in v3:
> - fix combphy error by moving sata0 to rk3568.dtsi
> - remove clock-names and interrupt-names
> changes in v2:
> - added sata0 + 1, but have only tested sata2
> ---
> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 +++++++++++++
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 26 ++++++++++++++++++++++++
> 2 files changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 5b0f528d6818..2a2f65899d47 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -8,6 +8,19 @@
> / {
> compatible = "rockchip,rk3568";
>
> + sata0: sata@fc000000 {
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc000000 0 0x1000>;
> + clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
> + <&cru CLK_SATA0_RXOOB>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&combphy0 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&power RK3568_PD_PIPE>;
> + status = "disabled";
> + };
> +
> pipe_phy_grf0: syscon@fdc70000 {
> compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
> reg = <0x0 0xfdc70000 0x0 0x1000>;
> @@ -114,3 +127,4 @@ power-domain@RK3568_PD_PIPE {
> #power-domain-cells = <0>;
> };
> };
> +
No need for new line here,
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 7cdef800cb3c..484c5ace718a 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -230,6 +230,32 @@ scmi_shmem: sram@0 {
> };
> };
>
> + sata1: sata@fc400000 {
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc400000 0 0x1000>;
> + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
> + <&cru CLK_SATA1_RXOOB>;
clock-names should be added. Also to bindings.
Best regards,
Krzysztof
