Hello,
On Wed, Jan 05, 2022 at 03:49:58PM -0500, Jeff Garzik wrote:
> On Tue, Jan 4, 2022 at 6:34 AM Paul Menzel <pmenzel@xxxxxxxxxxxxx> wrote:
>
> > [cc: +jeff, +tejun]
> >
> > void sata_phy_reset(struct ata_port *ap)
> > {
> > […]
> > /* wait for phy to become ready, if necessary */
> > do {
> > msleep(200);
> > sstatus = scr_read(ap, SCR_STATUS);
> > if ((sstatus & 0xf) != 1)
> > break;
> > } while (time_before(jiffies, timeout));
> > […]
> > }
> > ```
> >
>
> The piix did not have SCRs, as I recall, so it wouldn't apply to those
> chips. I don't recall further than that.
>
> Presumably just give those early chips a "needs delay" quirk, and then
> start testing newer chips to make sure they survive an immediate bitbang?
I don't remember exactly but most likely the sata_sil chips, I think. But,
yeah, the way forward would be converting it to a quirk and gradually lift
them with tests.
Thanks and happy new year.
--
tejun
