James Bottomley writes: > As Christoph said it would be stupid behaviour to invalidate the cache > after a hard reset because it would cause all deferred writes to fail. > The SCSI standards committee did initially assume manufacturers knew > this, but it was codified in SBC-4 and beyond with an explicit list of > conditions under which the write back cache could be lost, which > doesn't include hard reset. Wow... so a hard reset is in fact, not really a hard reset? I can see a soft reset maybe preserving the cache but I would expect a hard reset to be equal to pulsing the ^RST line. In fact, my understanding from reading the SATA spec was that the hard reset bus condition was intended to be detected by the PHY layer and pulse the ^RST signal to the higher level logic. Wait... SBC-4 applies to ATA disks too?
