Hi Miquel,
On Mon, Feb 25, 2019 at 11:58:26AM +0100, Miquel Raynal wrote:
> Baruch Siach <baruch@xxxxxxxxxx> wrote on Sun, 24 Feb 2019 07:29:09
> +0200:
>
> > On Fri, Feb 22 2019, Miquel Raynal wrote:
> > > There is no CP110 SATA port available on the 8040 Clearfog A8k, SATA
> > > may be used thanks to a mPCIe -> SATA extension board only. Hence, the
> > > cp1_sata0 node must be removed from the device tree.
> >
> > Not true. You can use the mini PCIe serdes as SATA directly if you
> > configure it as such. You only need to invert the serdes Rx pair
> > polarity. This is the default configuration for the Clearfog GT-8K CON3
> > mini-PCIe slot (CP1, lane #0) in current mainline U-Boot. I verified
> > that this setup works on Clearfog GT-8K.
> >
> > This patch would break mini PCIe direct SATA.
>
> Thanks for explaining, I am a little bit surprised that it actually
> uses the SATA host IP on CP110 but fine. So can you tell me which SATA
> port is used in this case? Because I will have to update the DT
> representation along with the CP110 changes.
According to the cp110_comphy_phy_mux_data[] array in U-Boot
drivers/phy/marvell/comphy_cp110.c, serdes 0 of CP110 can only be SATA1 (i.e.
the second port; first is SATA0).
Please Cc me on your next submission.
Thanks,
baruch
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