Hi,
On Thursday 19 November 2015 08:11 AM, Jaedon Shin wrote:
> The BCM7xxx ARM-based and MIPS-based platforms share a similar hardware
> block for AHCI SATA3.
>
> The BCM7425 is main chipset of MIPS-based 40nm class. The others have
> same PHY of AHCI block. The compatible string may use
> brcm,bcm7425-sata-phy.
>
> Signed-off-by: Jaedon Shin <jaedon.shin@xxxxxxxxx>
> Acked-by: Rob Herring <robh@xxxxxxxxxx>
> Tested-by: Florian Fainelli <f.fainelli@xxxxxxxxx>
> Acked-by: Brian Norris <computersforpeace@xxxxxxxxx>
> ---
> .../bindings/phy/brcm,brcmstb-sata-phy.txt | 1 +
> drivers/phy/Kconfig | 4 ++--
> drivers/phy/phy-brcmstb-sata.c | 24 ++++++++++++++++------
> 3 files changed, 21 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt
> index 7f81ef90146a..d87ab7c127b8 100644
> --- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt
> @@ -2,6 +2,7 @@
>
> Required properties:
> - compatible: should be one or more of
> + "brcm,bcm7425-sata-phy"
> "brcm,bcm7445-sata-phy"
> "brcm,phy-sata3"
> - address-cells: should be 1
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 7eb5859dd035..c6f4798ed3af 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -373,11 +373,11 @@ config PHY_TUSB1210
>
> config PHY_BRCMSTB_SATA
> tristate "Broadcom STB SATA PHY driver"
> - depends on ARCH_BRCMSTB
> + depends on ARCH_BRCMSTB || BMIPS_GENERIC
> depends on OF
> select GENERIC_PHY
> help
> - Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
> + Enable this to support the SATA3 PHY on 28nm or 40nm Broadcom STB SoCs.
> Likely useful only with CONFIG_SATA_BRCMSTB enabled.
>
> config PHY_CYGNUS_PCIE
> diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
> index 5de394f589c8..c8243581f196 100644
> --- a/drivers/phy/phy-brcmstb-sata.c
> +++ b/drivers/phy/phy-brcmstb-sata.c
> @@ -32,8 +32,14 @@
> /* Register offset between PHYs in PCB space */
> #define SATA_MDIO_REG_28NM_SPACE_SIZE 0x1000
>
> +/* The older SATA PHY registers duplicated per port registers within the map,
> + * rather than having a separate map per port.
> + */
> +#define SATA_MDIO_REG_40NM_SPACE_SIZE 0x10
> +
> enum brcm_sata_phy_version {
> BRCM_SATA_PHY_28NM,
> + BRCM_SATA_PHY_40NM,
> };
>
> struct brcm_sata_port {
> @@ -51,7 +57,7 @@ struct brcm_sata_phy {
> struct brcm_sata_port phys[MAX_PORTS];
> };
>
> -enum sata_mdio_phy_regs_28nm {
> +enum sata_mdio_phy_regs {
> PLL_REG_BANK_0 = 0x50,
> PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
>
> @@ -69,10 +75,14 @@ enum sata_mdio_phy_regs_28nm {
> static inline void __iomem *brcm_sata_phy_base(struct brcm_sata_port *port)
> {
> struct brcm_sata_phy *priv = port->phy_priv;
> - u32 offset;
> + u32 offset = 0;
>
> if (priv->version == BRCM_SATA_PHY_28NM)
> offset = SATA_MDIO_REG_28NM_SPACE_SIZE;
> + else if (priv->version == BRCM_SATA_PHY_40NM)
> + offset = SATA_MDIO_REG_40NM_SPACE_SIZE;
> + else
> + dev_err(priv->dev, "should not happen\n");
"invalid phy version" here?
Thanks
Kishon
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