Hello Stanislaw!
Thank you for patience and detailed explanations!
Sorry for long delays between answers, but I must work with another
projects.
* The NCS signal is not the same as CS1, CS2 ATA signals! It used only to
enable data bus transceiver U2.
Well, they are different signals but connected together. All of these are
controlled by NCS: CFCE1 (CS1), CFCE2 (CS2), CFRNW (DIR), CFCS0 (OE)
if SMC is configured in True IDE mode.
I must repeat again - NCS ("CFCS1" from schematic) are completely
different signal for different purpose, then A0, A1, A2, CS0, CS1.
It used only to enable data bus transceiver U2.
So, how in your opinion CS0 and CS1 are controlled? IMO there
are delivered from CFCE1 and CFCE2, which itself are delivered
from NCS. Here is corresponding quote from atmel documentation
you cited above:
"The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform"
This makes picture completely clean for me now.
I will publish new version patch for pata_at91.c.
Best regards!
--
Igor Plyatov
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